ATM cells are used to transfer data in high-speed asynchronous transfer mode (ATM) networks. The cells are described in Martin DePrycker, Asynchronous Transfer Mode: Solution for Broadband ISDN, Ellis Harwood Publishers, 2. ed., 1993. Standard ATM cells are 53 bytes in length. Each cell consists of a 48-byte body which contains the cell's data and a 5-byte header, which contains information used by the network to route the cell and by devices receiving the cell to interpret the cell. Cells are used both to carry control information for ATM networks and attached devices and to carry data between the attached devices.
A current problem in the design of ATM networks is the lack of low-cost, high-density ATM interfaces. Ultimately, ATM networks will directly provide ATM cells to and receive cells from low-cost consumer devices comparable to today's telephones, VCRs, CD players, or even smoke detectors. If ATM networks are to reach their full potential, simple, low-cost interfaces for transmitting and receiving ATM cells must be provided for devices such as those listed above. Additionally, ATM devices such as ATM switches require interfaces with a minimal number of pins to achieve high port densities.
A currently-popular example of a simple ATM interface is the UTOPIA interface described in UTOPIA, an ATM-PHY Interface Specification, Level 1, Version 2.01, The ATM Forum, Mar. 21, 1994. The interface is between a device at the ATM layer and a device at the physical (PHY) layer and has two parts: a transmit interface for transferring cells from the ATM layer to the PHY layer and a receive interface for transferring cells from the PHY layer to the ATM layer. Both interfaces require 8 lines to carry data signals and four lines to carry control signals. The transmit interface may additionally include two optional control lines. In the transmit interface, the four required control signals are the following:
TxSOC: Start of cell. Active high signal asserted by the ATM layer when the data lines contain the first valid byte of an ATM cell. PA1 TzEnb*: Enable. Active low signal asserted by the ATM layer during cycles when the data lines contain valid cell data. PA1 TxFull*/TxCalv: Full/cell available. For byte-level flow control, Txfull* is an active low signal from PHY to ATM layer, asserted by the PHY layer to indicate that a maximum of four more transmit data writes will be accepted. For cell-level flow control, TxClav is an active high signal from PHY to ATM layer, asserted by the PHY layer to indicate it can accept the transfer of a complete cell. PA1 TxClk: data transfer/synchronization clock provided by the ATM layer to the PHY layer for synchronizing transfers on TxData.
UTOPIA has a number of disadvantages which limit its use in low-cost devices or devices with high port densities. The first disadvantage is that a minimum of twelve bus lines are required, 8 for data and four for control signals. A second disadvantage is the complexity of the control signals, which include three flow control signals and a clock signal. A third disadvantage is that the UTOPIA interface is not symmetrical, that is, a device at the ATM layer must send to and receive from a device at the PHY layer, and cannot send to and receive from another device in the ATM layer. One consequence of this fact is that devices at the ATM layer cannot be directly connected to each other.
It is an object of the present invention to provide an ATM interface which is simple enough that switches using the interface can have high port densities and that low-cost devices can use the interface.